CURRICULUM VITAE

Updated on July 24, 2007.

CURRICULUM VITAE

Name : Y.N. SRIKANT

Designation : Professor

Department : Computer Science and Automation

email : srikant@csa.iisc.ernet.in

Phone : +91-80-2293 2771/2368

Fax : +91-80-2360 2911

Official Address : Dept. of Computer Science and Automation

Indian Institute of Science

Bangalore 560 012, India

Residential Address : NE-314, New E-Type Quarters

Indian Institute of Science Campus

Bangalore 560 012, India

Phone: +91-80-2360 3452

Educational Qualifications

B.E. (Electronics) Bangalore University, 1978.

M.E. (Automation) Indian Institute of Science (CSA), 1980.

Ph.D. (Computer Science) Indian Institute of Science (CSA), 1986.

Professional Activities

PC Chair, IISc Centenary Conference, MCDES 2008

Member, Editorial Advisory Board, SOFTWARE: Practice and Experience

PC Member, EMSOFT 2007

PC Member, VLSI Design 2007

PC Member, PACT 2003

Technical Program Chair, IEEE TENCON 2003

Member of Computer Society of India

Positions held at the Indian Institute of Science

_____________________________________________________

From To Designation

-----------------------------------------------------------------------------------------

13-Oct-1980 12-Oct-1985 Systems Programmer

13-Oct-1985 2-Jul-1987 Senior Scientific Officer

3-Jul-1987 2-Jul-1993 Assistant Professor

3-Jul-1993 2-Jul-1999 Associate Professor

3-Jul-1999 Present Professor

3-Jul-1999 10-Nov-2000 Associate Chairman

11-Nov-2000 3-Nov-2005 Chairman

______________________________________________________

Research Interests: Compiler design: compiler optimizations for energy reduction,

JIT compilation, profile-guided compiler optimizations,

safety analysis of binary code, compilation for multi-core and

multi-clock domain architectures.

Some Ongoing Research Projects

1. Energy-aware instruction scheduling.

2. Energy-aware cache reconfiguration.

3. Energy and time estimation of programs.

4. Partial flow sensitivity

5. An energy-aware compiler for sensor network nodes

6. Performance modelling of runtime systems.

Teaching Interests at graduate level:

1. Compiler Design

2. Topics in Compiler Design (advanced course)

3. Topics in Power-aware Computation

Sponsored Projects:

1. Co-Principal investigator of a DRDO sponsored project on

Robotics in which we developed a graphical simulation

environment for robotic applications (1985-90).

2. Principal Investigator of a DAE sponsored project on

A Parallelizer for Fortran programs for the BARC parallel

processing system (1995-99).

3. Principal Investigator of a Motorola India Electronics Ltd.

sponsored project on A Retargetable Compiler Tool Kit for

DSP architectures(project under Society for Innovation and

Development) (1997-98).

4. Principal Investigator of a Microsoft Sponsored project on

Investigations with .NET (this involved a JIT compiler for

the Microsoft IL on Linux) (July 2001-03).

5. Principal Investigator of a Microsoft Sponsored project on

Profile-Guided Optimizations with ROTOR (ROTOR is an open

source implementation of .NET) (2002-04).

6. Principal Investigator of a Microsoft Sponsored project on

Memory System Behavious of .NET Applications and A

Profile-Guided Garbage Collector for Rotor (2004-05).

7. Principal Collaborator of a DST/DAAD project with University

of Saarland (Saarbruecken, Germany) (2005-08).

8. A framework for power-aware programming

(Satyam Computers, 2005-06).

9. Program partitioing for massively multi-player games

(Satyam Computers, 2006-07).

Awards and recognitions:

(i) Karnataka State aware in 1972 for academic distionction in

PUC (III rank)

(ii) Karnataka State award in 1979 for academic distinction in

BE (I rank)

(iii) Gold medal by the Bangalore University in 1978 for academic

distinction in BE (I rank)

(iv) 'Young Scientist 1988' medal by Indian National Science

Academy for contributions in the area of compilers

Visiting Appointments:

1. Visiting Scientist, HP Labs, Palo Alto, USA, June-July, 2001.

2. Visiting Scientist, IBM Watson Research Center, New York, USA,

July, 2001.

3. Visiting Professor, Kaiserslautern University, Kaiserslautern,

Germany, June-July, 2002.

Research Thesis Guidance - Ph.D

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

1. N. Viswanathan, Algorithms for Parallel Compilation, Ph.D,

Jan. 1992.

2. R.K. Kulkarni, Towards Complete Automatic Code Generation, Ph.D,

Sept.1995.

3. U. Nagaraj Shenoy, Automatic Data Partitioning Using Hirearchical

Genetic Search, Ph.D, Sept. 1996.

4. R. Venugopal, Incremental Techniques for Code Generation Problems,

Ph.D, June 1997.

5. M.A. Dave, AMI - The Language and its Implementation, Ph.D, April 1997.

6. S.R.Prakash, Hyperplane Partitioning: An Approach to Global Data

Partitioning for Distributed Memory Machines, Ph.D, July 1998.

7. Vineet Kumar Paleri, An Environment for Automatic Generation of

Code Optimizers, Ph.D, July 1999 (jointly with Prof. Priti Shankar)

8. M. Bharat Kumar, Mining for Nurturers in Collaborative Networks, Ph.D

(May 2007).

9. Sujit Kumar Chakrabarti, A Programming environment for integrating and

implementing software components with heterogenous formal specifications,

Ph.D (ongoing).

10. K. Ananda Vardhan, Energy-efficient compilation for embedded processors,

Ph.D (ongoing).

11. Kapil Vaswani, Architectural support for programming languages and runtime

systems, Ph.D (ongoing).

12. Rahul Nagpal, Energy-efficient compilation for clustered processors (ongoing).

13. Subhajit Roy, Language Based Security Systems, Ph.D (ongoing).

14. R. Arun, Architectural Modelling for energy estimation, Ph.D (ongoing).

Research Thesis Guidance - M.Sc(Engg.)

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

1. M. Chelliah, A Compiler and Symbolic Debugger for Occam,

M.Sc.(Engg.), Aug. 1989.

2. M.A. Dave, A Parallelizing Compiler for Pascal,

M.Sc.(Engg.), Oct.1989.

3. Laeeq M. Khan, An Implementation of Cross Architecture

Procedure Call, M.Sc.(Engg.), June 1990.

4. K.A. Jasmeer, A Graphical Simulation Environment for

Robotics Applications, M.Sc.(Engg.), Aug 1990 (jointly

with Prof. M.R. Chidambara)

5. Y.V. Prasad, PEG-A Programming Environment Generator,

M.Sc.(Engg.). Sept. 1990.

6. R. Venugopal, Instruction Scheduling for RISC

Processors, M.Sc.(Engg.), June 1992.

7. U. Nagaraj Shenoy, An Automatic Parallelization Framework

for Multicomputers, M.Sc.(Engg.) Feb. 1993.

8. Abhay S. Kanhere, Implementation of Data Distribution and Parallelism

in HPF, M.Sc(Engg.), June 1997.

10. B.G. Suresh, RLtools: A Toolset for Visual Language Application

Development Based on Relational Grammars , M.Sc(Engg.),July 1997.

11. Suresh, Object-Oriented Software Engineering of a Compiler Prototyping

System, M.Sc(Engg.), July 1997.

12. R.Lakshminarayan, TriSL: A Software Architecture Description

Language and Environment, M.Sc(Engg.), July 1999.

13. S. Janaki, A Parallelizing Compiler for Fortran, M.Sc(Engg), July 1999.

14. D.V. Ravindra, Architecture Descriptions for Retargetable Code Generation,

M.Sc(Engg.), October 1999.

15. M.Bharat Kumar, Language Support for Exploiting Software Structure

Specifications, M.Sc(Engg.), March 2001.

15. Abhijit Mandal, Design and Implementation of a Java Virtual Machine,

M.Sc(Engg.), July 2000.

16. Sandeep Kohli, Slicing C++ Programs, M.Sc(Engg.), March 2001.

17. Ananda Vardhan, Language support for testing CORBA based programs

M.Sc(Engg.), November 2001.

18. V.Suresh, A framework for e-commerce in small communities,

M.Sc(Engg.), November 2001.

19. Kapil Vaswani, An adaptive Recompilation Framework for Rotor and Architectural

Support for Online Program Instrumentation, (M.Sc(Engg.), July 2003.

20. H.S. Gopalakrishna, Software Architectures for Radar Applications,

M.Sc(Engg.) , February 2004.

21. Devaraj Das, Design and Implementation of an Authentication and Authorization

Framework for a Nomadic Service Delivery System, M.Sc(Engg.), March 2003

(jointly with Geetha Manjunath, HP-ISO).

22. Rahul Nagpal, Integrated Scheduling for Clustered VLIW Processors,

(M.Sc(Engg.), December 2003.

23. Archana Ravindar, Cluster and Collect: Compile Time Optimization for Effective

Garbage Collection, M.Sc(Engg.), October 2005.

24. S.S. Shekhar, Object Cache: An Energy Efficient Cache Architecture, M.Sc(Engg.)

(July 2006).

25. Prachee Jindal, Compilation for embedded processors, M.Sc(Engg.), (ongoing).

=======================================================================

Book

Editor (jointly with Prof.Priti Shankar):

The Compiler Design Handbook: Optimization and Machine Code Generation

(Publication date: 26th September 2002)

Publishers: CRC Press

Forthcoming: The Compiler Design Handbook: Optimization and Machine Code Generation

(second edition, December 2007).

Book Chapters:

Scalar Compiler Optimizations on the SSA form and the Flowgraph, in

The Compiler Design Handbook: Optimization and Machine Code Generation,

Srikant, Y.N., and Shankar, P., CRC Press, September 2002.

Energy-aware Compiler Optimizations (jointly with Ananda Vardhan), in

The Compiler Design Handbook: Optimization and Machine Code Generation

(second ed., forthcoming, December 2007).

The Static Single Assignment Form: Construction and Application to Program Optimization

(jointly with Priti Shankar and J Prakash Prabhu), in

The Compiler Design Handbook: Optimization and Machine Code Generation

(second ed., forthcoming, December 2007).

Statistical and Machine Learning Techniques for Compiler Design

(jointly with Kapil Vaswani, P J Joseph, and Matthew Jacob), in

The Compiler Design Handbook: Optimization and Machine Code Generation

(second ed., forthcoming, December 2007).

=======================================================================

Journal Publications

1. Y.N. Srikant, D. Vidyasagar, and L.M. Patnaik, 'An

interactive graphics package for 2-D drawing and design',

Computers and Graphics, Vol.6, No.1, pp. 23-27,1982.

2. M.P. Subodh Kumar and Y.N. Srikant, 'Graphical simulation of

Petri nets', Computers and Graphics, Vol. 10, No. 3,

pp.225-228,1986.

3. Vijay Gehlot and Y.N. Srikant, 'An interpreter for SLIPS - an

applicative language based on lambda-calculus', Computer

Languages, Vol.11, No.1, pp. 1-13,1986.

4. Y.N. Srikant and Priti Shankar, 'A new parallel algorithm for

parsing arithmetic infix expressions', Parallel Computing,

4(1987), 291-304.

5. Y.N. Srikant and Priti Shankar, 'Parallel parsing of

programming languages', Information Sciences, vol.43, pp55-

83, 1987.

6. H.K. Haripriyan, Y.N. Srikant, and Priti Shankar, 'A compiler

writing system based on affix grammars', Computer Languages,

Vol. 13, No.1, 1988,pp. 1-11.

7. A Class of problems efficiently solvable on mesh-

connected computers including dynamic expression

evoluation, Inf.Proc. Letters, Vol.32, pp.305-311 ,1989.

(with A.M. Gibbons)

8. Incremental Attribute Evaluation through recursive

procedures, Computer Languages, Vol.14, No.4, pp 225-237,

1989. (with A.M. Murching)

9. Two dimensional object recognition using simulated Annealing,

Jl. of Ind. Inst. of Science, May-June 1990, Vol.70, pp. 197-

212. (with N.K. Sancheti and Y.V. Venkatesh)

10. Incremental Recursive Descent Parsing, Computer

Languages, Vol.15, No.4, pp.193-204, 1990. (with A.M.

Murching and Y.V. Prasad)

11. A Parallel algorithm for the minimization of finite

state automata, Intl. Jl. of Computer Mathematics,

Vol.132, pp.1-11, 1990.

12. Parallel Parsing of Arithmetic Expressions, IEEE

Trans.Computers, Vol.39, No.1, pp.130-132, 1990.

13. A Parallelizing Compiler for Pascal, Jl. of Ind.Inst. of

Science, Vol.71, pp.125-157, 1991. (with M.A. Dave)

14. Linda Subsystem on Transputers, Computer Languages,

Vol.18, No.2, pp.125-136, 1993. (with K.H. Shekhar)

15. Heuristic Chaining in Directed Acyclic Graphs,Computer

Languages, Vol. 19, No.3, pp.169-184, 1993. (with

R.Venugopal).

16. Parallel Incremental LR Parsing Computer languages,

Vol.20,No.3, pp.151-175, 1994. (with N.Vishwanathan)

17. Scheduling expression trees with register variables on

delayed load architectures, Microprocessors &

Microprogramming, Vol.40, pp.572-596, 1994.(with R.

Venugopal).

18. An automatic parallelization framework for multicomputers,

Computer Languages, Vol.20, No.3, pp.135-150, 1994.(with

Nagaraj Shenoy and V.P. Bhatkar, .

19. Scheduling Expression Trees with Reusable Registers on

Delayed-Load Architectures, Computer Languages, Vol.21, No.1,

pp 49-65, 1995 (with R. Venugopal).

20. An Incremental Basic Block Scheduler, Jl of Systems and Architecure,

1998 (with R.Venugopal).

21. The Complexity of Certain Incremental Code Generation Problems,

Int. Journal of Computer Mathematics, 1999(with R. Venugopal)

22. Automatic Data Partitioning by Hierarchical Genetic Search,

Journal of Parallel Algorithms and Architecture, 1999

(with Nagaraj Shenoy, V.P. Bhatkar, and Sandeep Kohli)

23. A Simple Algorithm for Partial Redundancy Elimination, SIGPLAN

Notices, December 1998(with Vineeth Kumar and Priti Shankar)

24. A Study of Automatic Migration of Programs across Java Event Models,

ACM SIGSOFT Notes, Vol.25, No.3, May 2000, pp 24-29 (with M. Bharath

Kumar and R. Lakshminarayanan).

25. Effective Parameterization of Architectural Registers for Register

Allocation Algorithms, SIGPLAN Notices, June 2000 (with D.V. Ravindra)

26. Partial Redundancy Elimination: A Simple, Pragmatic, and Provably

Correct Algorithm, Science of Computer Programming, 48 (2003), pp 1-20

(with Vineeth Kumar and Priti Shankar).

27. Hyperplane Partitioning: An Approach to Global Data Partitioning for

Distributed Memory Machines, The Journal of the Computer Society of

India, Vol.31, No.1, March 2001 (with S.R. Prakash).

28. Scheduling Expression Trees for Delayed Load Architectures, Journal of

Systems Architecture, 48 (2002) pp 151-173 (with R. Venugopal).

29. On The Use of Connector Libraries in Distributed Software Architectures,

ACM SIGSOFT Notes, Vol.27, No.1, 2002 (with M. Bharath Kumar and

R. Lakshminarayanan).

30. Dynamic Recompilation and Profile-guided Optimizations for a .NET JIT

Compiler, IEE Proc. Software, 150(5), October 2003, pp 296-302 ,

(Special issue on Rotor, jointly with Kapil Vaswani).

31. Pragmatic Integrated Scheduling for Clustered VLIW Architectures, Software:

Practice and Experience, 2007 (accepted for publication, jointly with Rahul Nagpal).

Conference Publications

1. D.Vidyasagar, Y.N. Srikant, and L.M. Patnaik, 'GRASS-A

Graphics software system for 2-D drawing and design', Proc.

CSI-81, Annual Convention, 1981.

2. T. Krishnaprasad, Y.N. Srikant, and Priti Shankar,'An

attribute grammar based compiler generator', Proc. CSI-85,

Annual Convention, 1985.

3. Bhaskar Rao and Y.N. Srikant,'LAPGEN-A lexical analyzer

program generator', Proc. CSI-85, Annual Convention, 1985.

4. M.P. Subodh Kumar and Y.N. Srikant, 'Graphical simulation of

Petri nets', Proc. CSI-85, Annual Convention, 1985.

5. Vijay Gehlot and Y.N. Srikant, 'A call-by-need interpreter

for an applicative language', Proc. Int. Conf. on

Informatics, 1985.

6. S. Muralidharan and Y.N. Srikant,'Design and implementation

of a compiler for EDISON using a compiler generator', Proc.

Int. Conf. on Informatics, 1985.

7. Y.N. Srikant and Priti Shankar, 'Data structures and

algorithms for binary tree traversals', Proc. CSI-85 Annual

Convention, 1985.

8. J. Ramesh Babu, Y.N. Srikant and S. Thirunarayanan,'A

compiler generator based on LALR(1) grammars', Proc. CSI-85,

Annual Convention, 1986.

9. Y.N. Srikant, Parallel parsing of arithmetic expressions',

Proc. IEEE International Conference on Parallel Processing,

1987.

10. Y.N. Srikant, 'Dynamic expression evaluation and its

implementation on a mesh-connected computer, Proc. IEEE

TENCON 87.

11. A Systolic Array Simulator Generator, Proc. Int.Conf.

on Informatics, 1988. (with C.R. Meenakshi Sundaram).

12. A Graphical Environment for Robotics Applications, Proc.

Intl. Symp. on Intelligent Robotics, pp.654-665, Jan.

1991.(with K.A.Jasmeer and M.R.Chidambara).

13. A Flexible Linda Subsystem on Transputers, Proc. Transputing

'91, 1991 (with K.H. Shekhar).

14. Parallel Attribute Evaluation, Supercomputing Symposium,

1991. (with N. Viswanathan)

15. Parallel Incremental LR Parsing, Int.Conf.Parallel

Processing, 1991. (with N. Viswanathan)

16. C2G2 : A Complete Code Generator Generator, Int. Conf.

Computer Systems and Education, 1994( with R.K.Kulkarni).

17. Distribution of Dynamic Data Structures on Multiprocessors,

Proc. Int.Conf. High Performance Computing, 1995. (with M.A.

Dave).

18. Communication Cost Estimation and Global Data Partitioning for

Distributed Memory Machines, Int.Conf.High Performance Computing,

1997 (with S.R.Prakash).

19. Hyperplane Partitioning: An Approach to Global Data Partitioning

for Distributed Memory Machines, Int.Par.Proc.Symposium, 1999

(with S.R. Prakash).

20. Formalizing Control Architectures for AMS, 2nd Nordic Workshop

on Software Architecture, NOSA'99, 1999 (with R. Lakshminarayanan).

21. LEADS: Language for Exploiting Architectural and Design Specifications,

Int.Computer Systems Conf., ICS'2000, R.O.C., October 2000, (with

M. Bharath Kumar).

22. Contextual Constraints - Breaking the "To Constrain or Not To Constrain"

Dilemma, Int.Computer Systems Conf., ICS'2000, R.O.C., October 2000,

(with R. Lakshminarayanan).

23. A Simple and Fast Scheme for Code Compression for VLIW Processors,

Data Compression Conference, 2003 (DCC’2003), Utah, March 2003 (jointly

with J.Prakash, C. Sandeep, and Priti Shankar).

24. Integrated Temporal and Spacial Scheduling for Extended Operand Clustered

VLIW Processors, ACM Conf. Computing Frontiers, 2004, pp457-470

(with Rahul Nagpal).

25. A Graph Matching Based Integrated Scheduling Framework for Clustered

VLIW Processors, Workshop on Compile and Run Time Techniques for

Parallel Processing, Int. Conf. Parallel Processing, 2004, pp530-537 (with

Rahul Nagpal).

26. Transition-Aware Scheduling: Increasing Continuous Periods in Resource

Units, ACM Conf. Computing Frontiers, 2005 (with K. Ananda Vardhan).

27. A Programmable Hardware Path Profiler, ACM Conf. Code Generation and

Optimization (CGO), 2005 (with Kapil Vaswani and Matthew T Jacob).

28. Static Analysis for Identifying and Allocating Clusters of Immortal Objects,

Int. Conf. .NET Technologies, 2005, pp13-22 (with Archana Ravindar).

29. The Best Nurturers in Computer Science, SIAM Int.Conf. on Data Mining,

2005 (with M. Bharath Kumar).

30. Specification Based Regression Testing Using Explicit State Space Enumeration,

International Conference on Software Engineering Advances (ICSEA), October

2006 (with Sujit Chakrabarti).

31. Compiler Assisted Leakage Energy Optimization for Clustered VLIW Architectures,

ACM EMSOFT, October 2006 (with Rahul Nagpal).

32. Exploring Energy-Performance Tradeoffs for Heterogeneous Interconnect Clustered

VLIW Processors, HiPC 2006, LNCS 4297 (with Rahul Nagpal).

33. Slice Switching: A Technique for Software Watermarking, Workshop on New Horizons

in Compilers, HiPC 2006 (with Subhajit Roy).

34. Microarchitecture Sensitive Empirical Models for Compiler Optimizations, ACM Conference

on Code Generation and Optimization, March 2007 (with Kapil Vaswani, P J Joseph,

and Matthew Jacob T).

35. Executable Analysis using Abstract Interpretation with Circular Linear Progressions,

ACM MEMOCODE, May-June 2007 (with Rathijit Sen).

36. WCET Estimation for Executables in the Presence of Data Caches, ACM EMSOFT, October 2007

(with Rathijit Sen).

37. INTACTE: An Interconnect Area, Delay, and Energy Estimation Tool for Microarchitectural

Explorations, ACM CASES, October 2007 (with Rahul Nagpal).

38. Compiler-Assisted Instruction Decoder Energy Optimization for Clustered VLIW Architectures,

HiPC, December 2007 (with Rahul Nagpal).

39. Register File Energy Optimization for Snooping Based Clustered VLIW Architectures,

SBAC-PAD, October 2007 (with Rahul Nagpal).

40. Partial Flow Sensitivity, HiPC, December 2007 (with Subhajit Roy).

M.E.Project Guidance

M1. M. Ramachandra Rao, A Parser for Modula, June 1983.

M2. Vijay Gehlot, An Interpreter for Slips - An Applicative

Language based on Lamda-Calculus, July 1984.

M3. T. Krishnaprasad, A Compiler Generator Based on Attributed

Translation Grammars, July 1984 (jointly with Priti

Shankar).

M4. S. Muralidharan, Design and Implementation of a Compiler for

EDISON Using a Compiler Generator, Jan. 1985.

M5. Rajeev Kanvar, A Code Generator for EDISON and a

Multiprocessor Simulator, Jan. 1987.

M6. Purandar Bhaduri, Code Generator Based on Tree Pattern

Matching, Jan. 1987.

M7. V. Sundar, Syntax-Directed Editor Generator, Jan. 1988.

M8. A.M. Murching, Incremental Algorithms for Compilation,

Jan. 1988.

M9. V. Ganeshan, Automatic Construction of Code Generators,

Jan.1988.

M10. Sanjay Jain, Syntax-Directed Editor as an Interface

for an Incremental Programming Environment, Jan. 1989.

M11. N.K. Sancheti, Algorithms in Computer Vision; Sequential

and Parallel Implementation, Jan. 1989.

M12. G. Ganeshan, Code Generator for Pascal Using Tree

Pattern Matching, Jan. 1989.

M13. G. Sreenivas, A Programming Environment for Actus, Jan.

1990.

M14. L.V. Nilesh, Implementation of OCCAM on a Multiprocessor,

Jan. 1990.

M15. Bhama Sridharan, Peephole Optimization and Global

M16. Vivek V. Gupta, Implementation of OCCAM on a Shared

memory multiprocessor, Jan. 1991.

M17. S. Geetha, Register Allocation Algorithms, A Study

and Implementation, Jan. 1991.

M18. Amitabh Dave, Code Generation for the Intel 80860, Jan.

1991.

M19. K.H. Shekhar, Design and Implementation of Linda on

Transputers, Jan. 1991.

M20. Sandhya Nayak, Implementation of an Auto-Scheduling

Compiler, Jan. 1991.

M21. Dibyendu Das, A Vectorizer for Pascal, Jan. 1992.

M22. Manoj Dighe, A Vectorizer for Pascal, Jan. 1993(continuation

of M15).

M23. K.S. Mohan Das, Incremental Dataflow Analysis and

M24. R.P. Banginvar, A code generator and Symbolic Debugger for

ACTUS, Jan. 1993.

M25. L.B. Shinde, An efficient code generator for i860, Jan.

1993.

M26. Bijendra Singh, A Debugger for LINDA, Jan.1994

M27. K. Sudha, Incremental Code Generation, July 1994.

M28. S.Kishore, An Efficient Code Generator for R4000, June 1995.

M29. Ajitesh Das, Building an Environment to Test Object-Oriented

Software, January 1996.

M30. A.M. Gondhiya, A Code Generator with Scheduler and Global

M31. M.Subba Rao, A CASE Tool based on the Fusion Methodology, January 1997.

M32. Anasua Bhowmik, Automatic Code Generating Environment, January 1997.

M33. Anoop Kumar, Integrated Register Allocation and Instruction Scheduling

January, 1997.

M34. G.R. Satyanarayana, Solve: A Tool for Testing Object-Oriented Programs,

July 1997.

M35. G. Venkatesha Murthy, Slicing C++ Programs, July 1997.

M36. Jai Anand, A CASE Tool to support Object-Oriented Analysis and Design for

Software Systems using Fusion Method, Jan 1998.

M37. G.Srinivas, Reverse Compilation of Assembly Code, Jan 1998.

M38. M.Balaraj, Automating the Process of Reviews using the Web, Jan 1998.

M39. N.R.Prashanth, Slicing Member Functions in C++ , Jan 1998.

M40. K.N.V.S.M. Lakshman, Just-In-Time Compilation of Java Byte Code,

April 1998.

M41. Biswajit Dutta, A Tool for Class and Cluster testing of Object-Oriented

Programs, July 1998.

M42. Jayesh Dixit, A Code Generator and Instruction Scheduler for DSP

microprocessors, July 1998.

M43. Vinayak Bhakta, Slicing Object-Oriented Programs, January 1999.

M44. E.Shreekar Varma, A Code Generator for a DSP microprocessor, April 1999.

M45. Milind Shingade, A Work-Flow Modelling Environment, April 1999.

M46. Rajendra K. Parida, A CASE Tool for UML-Based Modelling, July 1999.

M47. S.R. Biju, Automatic Code Generation from UML State-Chart Diagrams,

January 2000.

M48. E. Vijayakumar, Data Redistribution in a Parallelizing Compiler,

January 2000.

M49. N.V. Krishna, Type Verification of Java Byte Code, January 2000.

M50. Vinit Agrawal, Automatic Synthesis of UML State-Charts from Sequence

diagrams, January 2001.

M51. Srivalli, Generating C# code for Rational Rose UML diagrams,January 2002.

M52. Bharathi Shetty, Comparison of different PRE algorithms in gcc framework,

January 2003.

M53. Mohit Kumar, Implementation of SSA-based optimizations in gcc, January 2003 .

M54. Deepak Naik and Reetu Sabharwal, Code generation for the Itanium Processor,

January 2003 (jointly with Prof. Priti Shankar).

M55. J. Prakash and C. Sandeep, A Simple and fast scheme for code compression

For embedded VLIW processors, January 2003 (jointly with Prof. Priti Shankar).

M56. Amarnath Mullick and A Maitri, Software Watermarking, July 2004.

M57. Rathijit Sen, Worst case execution time analysis of executable code, July 2007.

M58. Sudipta Chattopadhyay, Cluster detection for efficient garbage collection, July 2007.